A low-phase-noise frequency synthesizer for single chip CMOS UHF RFID reader

Author

Zhang, Runxi ; Chen, Yihao ; Shi, Chunqi ; Lai, Zongshen

Author_Institution

IMCS, East China Normal Univ., Shanghai

Volume

3

fYear

2008

fDate

21-24 April 2008

Firstpage

1477

Lastpage

1480

Abstract

A novel fractional-N frequency synthesizer which is based on delta sigma modulator (DSM) and specialized for single-chip ultra-high frequency radio-frequency identification (UHF RFID) reader is proposed in this paper. The fractional-N synthesizer is implemented in 0.18 mum CMOS process. The phase noise of the fractional-N synthesizer is approximately -109 dBc/Hz and -129 dBc/Hz at 200 kHz and 1 MHz offset from 900 MHz operating frequency while drawing 9.6 mA from 1.8 V power supply. The synthesizer is evaluated by implementing it in a direct conversion RF front-end. The front-end features a noise figure of 3.5 dB and an input-referred third-order intercept point of 5 dBm.

Keywords

CMOS integrated circuits; UHF integrated circuits; delta-sigma modulation; frequency synthesizers; phase noise; radiofrequency identification; RF front-end; current 9.6 mA; delta sigma modulator; fractional-N frequency synthesizer; frequency 1 MHz; frequency 200 kHz; frequency 900 MHz; low-phase-noise frequency synthesizer; noise figure 3.5 dB; single- chip CMOS UHF RFID reader; single-chip ultra-high frequency radio-frequency identification reader; size 0.18 mum; voltage 1.8 V; Bandwidth; CMOS technology; Delta-sigma modulation; Frequency synthesizers; Phase frequency detector; Phase noise; Radio frequency; Radiofrequency identification; Signal to noise ratio; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology, 2008. ICMMT 2008. International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4244-1879-4

Electronic_ISBN

978-1-4244-1880-0

Type

conf

DOI

10.1109/ICMMT.2008.4540725

Filename

4540725