Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits

Author

Peng, Jeng-Jie ; Ker, Ming-Dou ; Jiang, Hsin-Chin

Author_Institution

Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

5

fYear

2002

fDate

2002

Abstract

A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a bulk CMOS chip, the core circuit blocks are always latchup sensitive due to a low holding voltage of the parasitic SCR path. The proposed latchup prevention methodology and circuit design can detect and stop the occurrence of latchup without any process modification or extra fabrication cost. It is suitable for whole-chip latchup prevention of bulk CMOS integrated circuits. This proposed latchup current self-stop methodology and circuit have been verified in a 0.5-μm 1P3M bulk CMOS process.

Keywords

CMOS integrated circuits; fault currents; integrated circuit design; integrated circuit reliability; integrated circuit testing; 0.5 micron; 1P3M bulk CMOS process; bulk CMOS chip; bulk CMOS integrated circuits; circuit damage prevention; fabrication cost; latchup current self-stop circuit design; latchup current self-stop methodology; latchup sensitive core circuit blocks; parasitic SCR path holding voltage; process modification; whole-chip latchup prevention; CMOS integrated circuits; CMOS process; Circuit synthesis; Costs; MOS devices; Power supplies; Silicon; Switches; Thyristors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010759

Filename

1010759