CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits

Author

Min, Kyeong-Sik ; Kim, Young-Hee ; Ahn, Jin-Hong ; Chung, Jin-Yong ; Sakurai, Takayasu

Author_Institution

Center for Collaborative Res., Univ. of Tokyo, Japan

Volume

5

fYear

2002

fDate

2002

Abstract

To overcome the problems of the modified Dickson pump like NCP-2, a new pump (CCTS-1) where simple voltage doublers are cascaded in series and each of them has cross-coupled configuration is studied in this paper for possible use in low-voltage EEPROMs and DRAMs. Though this concept of cascading doublers has been previously proposed, it is firstly addressed in this paper that CCTS-1 has the lower gate-oxide stress, the improved voltage pumping gain, and the better power efficiency than NCP-2 so that CCTS-1 can be more suitable for the multi-stage pump in particular at low V_CC. In addition, CCTS-2 is proposed to overcome the degraded body-effect of CCTS-1 without using boosted clocks when the stage number is large.

Keywords

CMOS memory circuits; DRAM chips; EPROM; cascade networks; dielectric thin films; internal stresses; low-power electronics; voltage multipliers; CCTS-1; CCTS-2; CMOS charge pumps; boosted clocks; cascaded voltage doublers; cross-coupled charge transfer switches; degraded body-effect; gate-oxide stress; low-voltage DRAM; low-voltage EEPROM; low-voltage memory circuits; modified Dickson pump; multi-stage pump; power efficiency; voltage pumping gain; CMOS memory circuits; Charge pumps; Charge transfer; Clocks; Degradation; EPROM; Stress; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010761

Filename

1010761