DocumentCode
1813943
Title
A 10 ns, 4000 gate, 160 pin CMOS EPLD developed on a 0.8 μm process
Author
Patel, Rakesh ; Wong, Myron ; Reese, Dirk ; Costello, John ; Turner, John
Author_Institution
Altera Corp., San Jose, CA, USA
fYear
1993
fDate
9-12 May 1993
Abstract
The 160-pin EPM7192, an erasable programmable logic device (EPLD) with a system operating frequency in excess of 100 MHz, is described. This 192 macrocell device is the fastest EPLD at this logic density. The input to output propagation delay for this device was measured to be 9.8 ns. The clock to output propagation delay was clocked at 4 ns. This device uses a combination of architectural, process, and circuit improvements to achieve high performance and logic densities. The EPM7192 is implemented on a 0.8-μm CMOS-EEPROM (electrically erasable programmable read-only memory) technology
Keywords
programmable logic arrays; 0.8 micron; 10 ns; 160 pin; 192 macrocell device; 4000 gate; CMOS EPLD; CMOS-EEPROM; EPM7192; erasable programmable logic device; global signals; high performance; programmable interconnect array; CMOS logic circuits; CMOS technology; Clocks; Frequency; Logic circuits; Logic devices; Macrocell networks; PROM; Programmable logic devices; Propagation delay;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0826-3
Type
conf
DOI
10.1109/CICC.1993.590580
Filename
590580
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