DocumentCode
1813966
Title
PREP benchmarks for programmable logic devices
Author
McCarty, Dennis ; Faria, Donald ; Alfke, P.
Author_Institution
Actel Corp., Sunnyvale, CA, USA
fYear
1993
fDate
9-12 May 1993
Abstract
The authors describe a set of benchmark circuits and implementation methodology for measuring logic capacity and speed performance in programmable logic devices (PLDs). PLDs include complex PLDs and field programmable gate arrays (FPGAs). The PREP (Programmable Electronic Performance Corporation) benchmarks were developed for users of PLDs to evaluate different architectures and devices for logic capacity and speed performance using common logic functions and a standard methodology
Keywords
programmable logic devices; PREP benchmarks; benchmark circuits; complex PLDs; data path; field programmable gate arrays; filler circuit; implementation methodology; large state machine; logic capacity; logic functions; programmable logic devices; small state machine; speed performance; timing; Clocks; Field programmable gate arrays; Integrated circuit measurements; Logic circuits; Logic design; Logic devices; Programmable logic arrays; Programmable logic devices; Routing; Velocity measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0826-3
Type
conf
DOI
10.1109/CICC.1993.590581
Filename
590581
Link To Document