PAS: A stand alone placement annotation system for high speed designs

To predict the high-speed electronic circuit performance in the early physical design stage, a stand-alone placement annotation system (PAS) which uses efficient and accurate models for both output drivers and interconnects has been developed. The placement annotation algorithm is presented, the placer and the placement checker in PAS are addressed, and experimental results are given. PAS is implemented in C using a Motif graphical user interface. Using actual production ECL (emitter coupled logic), TTL (transistor transistor logic), and BiCMOS designs, placement annotation delays are compared with back annotation delays from the fully routed design. The interconnect delay numbers given by placement annotation are within a 5% range of the actual back annotation number for more than 95% of the nets in a typical design