Modifying the netlist after placement for performance improvement

A postplacement netlist modifier which improves the performance of a placed netlist is presented. Iterative technology remapping operations customize the most critical path timing for physical wire capacitances that are unique to a standard-cell placement. The improvement is reached through three operations: buffer tree resynthesis, gate drive resizing, and gate reconnection. Results show up to a 13% reduction in circuit timing for MCNC benchmarks that have already been optimized at the logic level for timing