• DocumentCode
    1816860
  • Title

    Power distribution synthesis for analog and mixed-signal ASICs in RAIL

  • Author

    Stanisic, Balsha R. ; Rutenbar, Rob A. ; Carley, L. Richard

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    1993
  • fDate
    9-12 May 1993
  • Abstract
    The authors present new power distribution synthesis techniques that can handle realistic analog and mixed-signal performance concerns. The key ideas are to employ asymptotic waveform evaluation techniques to reduce complex macro, substrate, and package electrical models to accurate, low-order analytical expressions that can be quickly evaluated by a simulated annealing optimizer that selects and sizes the power bus topology while accommodating DC, AC, and transient constraints. RAIL, a new tool for power distribution, is used for this purpose. Experimental results demonstrate the importance of optimizing both topology selection and sizing, and the critical need to include transient as well as DC constraints during synthesis
  • Keywords
    network topology; AC constraints; DC constraints; RAIL tool; analogue ASIC; asymptotic waveform evaluation; mixed-signal ASICs; power bus topology; power distribution synthesis; simulated annealing optimizer; topology selection; topology sizing; transient analysis; transient constraints; Application specific integrated circuits; Circuit synthesis; Constraint optimization; Current density; Power distribution; Rails; Semiconductor device noise; Substrates; Topology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0826-3
  • Type

    conf

  • DOI
    10.1109/CICC.1993.590740
  • Filename
    590740