• DocumentCode
    1817211
  • Title

    High performance BiCMOS technology

  • Author

    Liu, T.M. ; Chiu, T.Y. ; Swartz, R.G.

  • Author_Institution
    AT&T Bell Lab., Holmdel, NJ, USA
  • fYear
    1993
  • fDate
    9-12 May 1993
  • Abstract
    The authors describe the process integration issues of high-performance BiCMOS technologies intended to be used not only in high-density digital applications but also in high speed ECL (emitter coupled logic) and mixed analog/digital signal applications. In particular, they describe a half-micron super-self-aligned BiCMOS technology with bipolar fmax of 34 GHz and a CMOS gate delay of 50 psec. Circuit applications for multi-gigahertz communication are presented to show the potential of high-performance BiCMOS technology
  • Keywords
    BiCMOS logic circuits; 34 GHz; 50 ps; CMOS gate delay; high speed ECL; high-density digital applications; high-performance BiCMOS technology; isolation; low power design; mixed analog-digital signal applications; multi-gigahertz communication; process integration; super-self-aligned; BiCMOS integrated circuits; CMOS process; CMOS technology; Carbon capture and storage; Circuit optimization; Delay; Microprocessors; Optical design; Random access memory; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0826-3
  • Type

    conf

  • DOI
    10.1109/CICC.1993.590761
  • Filename
    590761
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1817211