A 64 kB BiCMOS cache controller and memory (CCM)

Author

Kobayashi, Toru ; Nojima, Hiromi ; Konno, Minoru ; Igarashi, Masahiro ; Kamano, Shoichi ; Kobayashi, Keigo ; Shimoda, Kouichi ; Shidei, Tsunaaki ; Kumazawa, Mutsumi ; Mori, Toshitaka ; Kurotsu, Satoru

Author_Institution

OKI Electric Industry Co., Ltd., Tokyo, Japan

fYear

1993

fDate

9-12 May 1993

Abstract

The authors describe the cache controller and memory (CCM) for the external cache of a microprocessor. This CCM integrates 64 kB cache memory, TAG, and control logic using 0.7-μm BiCMOS technology. Four-way set-associative mapping and an LRU (least recently used) replacement algorithm are adopted for the cache. The chip is 14.8×15.0 mm² and dissipates 3.0 W at 50 MHz. This CCM also supports copy-back protocol and bus snoop function for multiprocessor systems and has several system configuration modes for flexibility in systems. TAG and cache memory have parity bit for high reliability systems

Keywords

BiCMOS memory circuits; 0.7 micron; 3 W; 50 MHz; 64 kByte; BiCMOS cache controller; TAG memory; architecture; bus snoop function; control logic; copy-back protocol; external cache; four-way set-associative mapping; least recently used replacement algorithm; memory; microprocessor; multiprocessor systems; redundancy; BiCMOS integrated circuits; Cache memory; Central Processing Unit; Detectors; Industrial control; Logic; Protocols; Read-write memory; System buses; Technical Activities Guide -TAG;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590768

Filename

590768