A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability

Author

Lines, Valerie ; McKenzie, Robert ; Oh, Hak-June ; Pyeon, Hong-Beom ; Dunn, Matthew ; Palapar, Susan ; Coleman, Susan ; Nyasulu, Peter ; Mai, Tony ; Pike, Seanna ; McCready, John ; Defazio, Jody ; Kim, Jin-Ki ; Penchuk, Robert ; Greenfield, Zvika ; Lange,

Author_Institution

MOSAID Technol. Inc., Kanata, Ont., Canada

fYear

2005

fDate

5-5 Aug. 2005

Firstpage

47

Lastpage

51

Abstract

A 1GHz 2Mb embedded DRAM macro and an associated fully programmable BIST block have been designed in a 90nm logic based technology. The DRAM macro has 128-bit I/O, sixteen banks, 1 ns interleaved operation, 4ns random access read pipeline, and an early write scheme. The BIST is used for at-speed testing of the DRAM macro and can accumulate fail data for redundancy repair and bitmap generation. It can be cascaded and shared between memory macrocells.

Keywords

DRAM chips; built-in self test; embedded systems; integrated circuit testing; 1 GHz; 1 ns; 2 Mbit; 4 ns; 90 nm; at-speed bitmap capability; at-speed testing; bitmap generation; built-in self-test; early write scheme; embedded DRAM; interleaved operation; memory macrocells; programmable BIST; random access read pipeline; redundancy repair; Automatic testing; Built-in self-test; Circuit testing; Fuses; Logic design; Logic devices; Logic testing; Pipelines; Random access memory; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on

Conference_Location

Taipei

ISSN

1087-4852

Print_ISBN

0-7695-2313-7

Type

conf

DOI

10.1109/MTDT.2005.5

Filename

1498202