Representations of logic functions using QRMDDs

Author

Nagayama, Shinobu ; Sasao, Tsutomu ; Iguchi, Yukihiro ; Matsuura, Munehiro

Author_Institution

Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan

fYear

2002

fDate

2002

Firstpage

261

Lastpage

267

Abstract

This paper considers quasi-reduced multi-valued decision diagrams with k bits (QRMDD(k)s) to represent two-valued logic functions. It shows relations between the numbers of nodes in QRMDD(k)s and values of k for benchmark functions; an upper bound on the number of nodes in the QRMDD(k); difference between the upper bound and the number of nodes in the QRMDD(k)s for random functions; and the amount of total memory, evaluation time, and area-time complexity for QRMDD(k)s. Experimental results using standard benchmark functions show that the area-time complexity takes its minimum when k is between 3 and 6

Keywords

computational complexity; decision diagrams; multivalued logic; area-time complexity; benchmark functions; evaluation time; experimental results; logic function representation; memory; quasi-reduced multi-valued decision diagrams; random functions; two-valued logic functions; upper bound; Area measurement; Bismuth; Boolean functions; Character generation; Computer science; Cost accounting; Data structures; Logic functions; Microelectronics; Upper bound;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on

Conference_Location

Boston, MA

Print_ISBN

0-7695-1462-6

Type

conf

DOI

10.1109/ISMVL.2002.1011097

Filename

1011097