DocumentCode
1821716
Title
A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits
Author
Hosokawa, Toshinori ; Date, Hiroshi ; Muraoka, Michiaki
Author_Institution
Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan
fYear
2002
fDate
2002
Firstpage
328
Lastpage
335
Abstract
This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.
Keywords
VLSI; automatic test pattern generation; design for testability; hierarchical systems; integrated circuit design; logic CAD; modules; DFT; RTL data path circuits; compacted test table; heuristic algorithm; hierarchical test generation; Circuit synthesis; Circuit testing; Design for testability; Design methodology; Hardware; Logic circuits; Logic design; Logic testing; Multiplexing; Semiconductor device testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN
0-7695-1570-3
Type
conf
DOI
10.1109/VTS.2002.1011161
Filename
1011161
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