Delay models for the sea-of-wires array synthesis system

This paper presents two simple, accurate and efficient delay models, the static delay model and the dynamic delay model, to support performance optimization of VLSI Sea-of-Wires Arrays (SWA). The SWA delay model treats each distributed gate as an attribute-based primitive gate with different internal and external connection wires. Instead of solving differential equations, the SWA model determines delays by lookup from a multi-dimensional table. Only a few microseconds of execution time are needed per gate. The propagation delay along a circuit path is the sum of the delay segments of distributed gates in the path. The critical path of an SWA design can be identified with an O(n) timing analysis algorithm. For most AHPL Benchmarks, the table-lookup method achieves 5 orders of magnitude speedup over SPICE for the same circuits with error margin less than 7%