A 622/155 mbps ATM line terminator mono-chip

Author

Nava, M. Diaz ; Belot, D. ; Delerue, P. ; Bulone, J.

Author_Institution

SGS-Thomson, Crolles, France

fYear

1995

fDate

6-9 Mar 1995

Firstpage

173

Lastpage

178

Abstract

The ATM line terminator mono-chip (LTM) provides a highly integrated and cost effective implementation of the physical layer of the ATM network for cell-based interface. The LTM was designed in a BiCMOS process allowing the merging of CMOS data processing together with the high speed transceiver functions requested by ITU-T bit rates of 622.08 and 155.52 mbps. Internal design for testability provides easy testing at device and system levels

Keywords

BiCMOS digital integrated circuits; asynchronous transfer mode; design for testability; digital communication; digital signal processing chips; electronic switching systems; integrated circuit testing; transceivers; 155 Mbit/s; 622 Mbit/s; ATM line terminator mono-chip; ATM network; ATM physical layer; BiCMOS process; CMOS data processing; DFT; ITU-T bit rates; cell-based interface; design for testability; high speed transceiver functions; BiCMOS integrated circuits; Bit rate; CMOS process; Costs; Data processing; Design for testability; Merging; Physical layer; System testing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1995. ED&TC 1995, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-7039-8

Type

conf

DOI

10.1109/EDTC.1995.470401

Filename

470401

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1821883