Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC

The design and implementation of an input/output processor for an ATM switch are described. This IC was realized on a 0.7 μm BiCMOS technology. To manipulate ATM cells at a frequency of 311 MHz (STM16) at the I/O of the chip, ECL blocks were employed. The core of the chip is composed of CMOS cells that run at a maximum clock speed of 65 MHz. Pure analog blocks were not needed. The CMC is capable of functioning in two different modes: 1. The CM mode, in which 8 bit wide ATM cells are converted to a custom parallel format (microcells). 2. The MC mode, in which microcells are converted into 8 bits wide ATM cells. Two different set of pads were used, ECL and conventional CMOS pads. The circuit complexity is 320 K transistors and its die size is 224 mm². It is encapsulated in a CPGA-319 pin package and dissipates 8.2 watts at 311 MHz