DocumentCode
1824413
Title
Efficient multi-domain ESD analysis and verification for large SoC designs
Author
Chang, Norman ; Liao, Youlin ; Li, Ying-Shiun ; Johari, Pritesh ; Sarkar, Aveek
Author_Institution
Apache Design Solutions, Inc., San Jose, CA, USA
fYear
2011
fDate
11-16 Sept. 2011
Firstpage
1
Lastpage
7
Abstract
An efficient layout-based multi-domain ESD analysis and verification method has been developed for large SoC designs containing thousands of bumps. A fast resistance and current density check for ESD discharging paths across multiple diodes/clamps represented as I-V curves is performed, including on-chip signal/power/ground/package grid. Real application examples are shown.
Keywords
current density; electrostatic discharge; system-on-chip; SoC designs; current density check; fast resistance check; multidomain electrostatic discharge; on-chip signal-power-ground-package grid; system-on-chip; Clamps; Current density; Discharges; Electrostatic discharge; Layout; Resistance; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
Conference_Location
Anaheim, CA
ISSN
Pending
Electronic_ISBN
Pending
Type
conf
Filename
6045604
Link To Document