VLSI Circuits for Accurate Motion Estimation

Author

Perri, Stefania ; Corsonello, Pasquale ; Cocorullo, Giuseppe

Author_Institution

Dept. of Electron. Comput. Sci. & Syst., Univ. of Calabria, Arcavacata di Rende, Italy

fYear

2010

fDate

18-25 July 2010

Firstpage

23

Lastpage

27

Abstract

This paper presents VLSI circuits for Variable Block-Size Motion Estimation based on the Multiplication-Free Weighted SAD. Comparisons with existing SAD-based circuits demonstrate that higher accuracy is achieved without compromising speed performance, but resources requirements can significantly increase. Using a 90 nm 1 V CMOS technology, a running frequency higher than 1 GHz and an average power consumption lower than 100 uW/MHz are reached.

Keywords

CMOS integrated circuits; VLSI; motion estimation; video signal processing; CMOS technology; VLSI circuits; average power consumption; image processing; multiplication-free weighted SAD circuit; running frequency; size 90 nm; sum of absolute difference circuit; variable block-size motion estimation; video processing; voltage 1 V; Accuracy; Clocks; Computer architecture; Current measurement; Motion estimation; Pixel; Silicon; Image and Video Processing; Motion Estimation; VLSI circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Circuits, Electronics and Micro-Electronics (CENICS), 2010 Third International Conference on

Conference_Location

Venice

Print_ISBN

978-1-4244-7535-3

Type

conf

DOI

10.1109/CENICS.2010.11

Filename

5558170