DocumentCode
1825376
Title
Delay testing for non-robust untestable circuits
Author
Cheng, Kwang-Ting ; Chen, Hsi-Chuan
Author_Institution
AT&T Bell Lab., Murray Hill, NJ, USA
fYear
1993
fDate
17-21 Oct 1993
Firstpage
954
Lastpage
961
Abstract
Recently published results have shown that, for many circuits, only a small percentage of path delay faults is robust testable. Among the robust untestable faults, a significant percentage of them is not non-robust testable either. In this paper, we take a closer look at the properties of these non-robust untestable faults with the goal of determining whether and how these faults should be tested
Keywords
delays; fault diagnosis; fault location; logic testing; redundancy; delay testing; logic testing; nonrobust untestable circuits; path sensitisation; redundant path delay fault; robust untestable faults; Benchmark testing; Circuit faults; Circuit optimization; Circuit testing; Delay; Electrical fault detection; Fault detection; Fault diagnosis; Robustness; Sufficient conditions;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1993. Proceedings., International
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-1430-1
Type
conf
DOI
10.1109/TEST.1993.470604
Filename
470604
Link To Document