Switch-level ATPG using constraint-guided line justification

This paper explores a test pattern generation problem for switch-level combinational circuits. In test generation for switch-level circuits, constraints on assignable logic values can be introduced due to the difference between the implicated logic values and the justifiable logic values of a logic element. Therefore, identifying unjustifiable logic values as early as possible would greatly accelerate the switch-level test generation. For this, a new logic value system called taboo logic value is proposed to represent the unjustifiable logic values of a node. Also, a new switch-level ATPG system is developed which employs a constraint-guided line justification method using taboo logic value. Finally, experimental results on various types of circuits demonstrate the efficiency of the proposed approach and the possibility of the practical application to large switch-level circuits