A 3.3-V 18-bit digital audio Sigma-Delta modulator in 0.6-μm CMOS

Author

Yavari, Mohammad ; Hasanzadeh, Mohammad Reza ; Talebzadeh, Jafar ; Shoaei, Qmid

Author_Institution

Electr. & Comput. Eng. Dept., Tehran Univ., Iran

Volume

2

fYear

2002

fDate

2002

Abstract

This paper presents a 3.3-V, 18-bit Sigma-Delta modulator for digital audio, which has been simulated in a 0.6 μm double poly, triple metal CMOS process using poly-poly capacitors in all process corners and considering ± 10 % power supply and -40°C to 85°C temperature ranges. The integral gain coefficients of a 2-2 cascaded modulator have been developed for achieving higher overload level factor that is needed for high-resolution noise limited performance modulators. Simulation results give SNDR of 111 dB and 110 dB in typical and worst case, respectively with considering of the circuit noise.

Keywords

CMOS integrated circuits; audio signal processing; cascade networks; integrated circuit noise; sigma-delta modulation; -40 to 85 degC; 0.6 micron; 18 bit; 3.3 V; DPTM CMOS process; SNDR; cascaded modulator; circuit noise; digital audio; gain coefficient; overload level factor; poly-poly capacitor; sigma-delta modulator; CMOS process; Capacitors; Circuit noise; Circuit simulation; Delta-sigma modulation; Digital modulation; Noise level; Performance gain; Power supplies; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1011434

Filename

1011434