Efficient IP routing table VLSI design for multigigabit routers

The routing table lookup becomes a great bottleneck when multi-gigabit links are required in today´s network routers. Hence, we propose a lookup scheme that can efficiently handle IP routing lookup, insertion and deletion inside the routing table. By introducing memory reduction and the novel skip function, we have successfully reduced the required memory size to about 0.59 Mbytes. The routing table VLSI design was carried out. It can achieve one route lookup for every memory access using pipeline implementation. Timemill post-layout simulation results show that the chip can furnish approximately 30×10⁶ lookups/s, and thus it can support up to 30 Gbits/s link speed when the frame size is 1000 bits. In addition, our design can be easily scaled from IPv4 to IPv6.