DocumentCode
1827648
Title
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)
fYear
2003
fDate
6-6 June 2003
Abstract
The following topics are dealt with: real challenges and solutions for validating System-on-Chip, reshaping EDA for power, design for manufacturability and global routing, design analysis techniques, embedded hardware design case studies, emerging design and tool challenges in RF and wireless applications, power grid analysis and optimization, low-power embedded system design, cyclic and non-cyclic combinational synthesis, managing leakage power, timing-oriented placement, issues in partitioning and design space exploration for codesign, nanotechnology: design implications and CAD challenges, simulation coverage and generation for verification, tool support for architectural decisions in embedded systems, new topics in logic synthesis, coping with variability: the end of deterministic design, testbench, verification and debugging: practical considerations, delay and noise modeling in the nanometer regime, modeling issues in the design of embedded systems, how application/technology evolutions will shape classical EDA, SAT and BDD algorithms for verification tools, elements of functional and performance analysis, nonlinear model order reduction, novel techniques in high-level synthesis, mixed-signal design and simulation, novel self-test methods, technology mapping, buffering, and bus design, compilation techniques for reconfigurable devices, architectural power estimation and optimization, techniques for reconfigurable logic applications, test and diagnosis for complex designs, highlights of ISSCC: high-speed heterogenous design techniques, highlights of ISSCC and the design of state-of-the-art microprocessors, high frequency interconnect modeling, novel approaches in test cost reduction, retargetable tools for embedded software, ASIC design in nanometer era - dead or alive?, floorplanning and placement, advances in SAT, novel design methodologies and signal integrity, memory optimization for embedded systems, design automation for quantum circuits, energy-aware sys
Keywords
circuit layout CAD; electronic design automation; integrated circuit design; system-on-chip; ASIC design; BDD algorithm; EDA; RF application; SAT; application specific integrated circuit; architectural power estimation; binary decision diagram; cyclic combinational synthesis; design space exploration; electronic design automation; embedded system design; hardware design; interconnect noise avoidance; logic synthesis; memory optimization; noncyclic combinational synthesis; nonlinear model order reduction; power grid analysis; quantum circuit; reconfigurable device; reconfigurable logic application; retargetable tool; satisfiability; self-test method; slew rate prediction; state-of-the-art microprocessor; system-on-chip; technology mapping; test cost reduction; timing-oriented placement; wireless application; Design automation; Integrated circuit design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings
Conference_Location
Anaheim, CA
Print_ISBN
1-58113-688-9
Type
conf
DOI
10.1109/DAC.2003.1218765
Filename
1218765
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