Hierarchical Composite Regular Parallel Architecture

Author

Manjunathaiah, M.

Author_Institution

Comput. Sci. & Inf., Univ. of Reading Reading, Reading, UK

fYear

2009

fDate

June 30 2009-July 4 2009

Firstpage

253

Lastpage

256

Abstract

The design space of emerging heterogeneous multi-core architectures with re-configurability element makes it feasible to design mixed fine-grained and coarse-grained parallel architectures. This paper presents a hierarchical composite array design which extends the current design space of regular array design by combining a sequence of transformations. This technique is applied to derive a new design of a pipelined parallel regular array with different dataflow between phases of computation.

Keywords

parallel architectures; pipeline processing; reconfigurable architectures; coarse-grained parallel architecture; design space; fine-grained parallel architecture; heterogeneous multicore architecture; hierarchical composite array design; hierarchical composite regular parallel architecture; pipelined parallel regular array; reconfigurable architecture; Computer architecture; Concurrent computing; Embedded computing; Equations; High performance computing; Parallel architectures; Parallel processing; Phased arrays; Pipeline processing; Zinc; space-time mapping; systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Computing, 2009. ISPDC '09. Eighth International Symposium on

Conference_Location

Lisbon

Print_ISBN

978-0-7695-3680-4

Type

conf

DOI

10.1109/ISPDC.2009.41

Filename

5284345