PSRR of bridge-tied load PWM Class D Amps

Author

Ge, Tong ; Chang, Joseph S. ; Shu, Wei

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

fYear

2008

fDate

18-21 May 2008

Firstpage

284

Lastpage

287

Abstract

In this paper, the effects of power supply noise, qualified by power supply rejection ratio (PSRR), on two types of bridge-tied load (BTL) pulse width modulation (PWM) class D amps (denoted as Type-I BTL and Type-II BTL respectively) are investigated and the analytical expressions for PSRR of the two designs derived. The derived analytical expressions are verified by means of HSPICE simulations. The relationships derived herein provide good insight to the design of BTL class D amps, including how various parameters may be varied/optimized to meet a given PSRR specification. Furthermore, the PSRR of the two BTL Class D amps are compared against the single-ended class D amp, and the former designs show superior PSRR compared to the latter.

Keywords

SPICE; amplifiers; bridge circuits; circuit noise; pulse width modulation; HSPICE simulations; bridge-tied load PWM class D amps; power supply noise; power supply rejection ratio; pulse width modulation; Analytical models; Design engineering; Digital modulation; Feedback loop; Power engineering and energy; Power supplies; Pulse width modulation; Pulsed power supplies; Signal to noise ratio; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4541410

Filename

4541410