An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networks

Author

Abe, Takashi ; Morie, Takashi ; Satou, Kazutoshi ; Nomasaki, Daisuke ; Nakamura, Shigenari ; Horiuchi, Yoichiro ; Imamura, Kousuke

Author_Institution

Panasonic Corp., Yokohama, Japan

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

This paper presents an ultra-low-power 2-step wake-up receiver for the IEEE 802.15.4g. The receiver is composed of an ultra-low-power energy-detection receiver (EDRX) and an address-detection FSK receiver (ADRX). The ADRX is activated only when the EDRX detects a wakeup packet which minimizes power consumption. Fabricated in a 65 nm CMOS process, the receiver achieves an excellent receiver sensitivity of -87 dBm while consuming only 45.5 μW average power.

Keywords

CMOS integrated circuits; Zigbee; frequency shift keying; low-power electronics; radio receivers; sensitivity; wireless sensor networks; ADRX; CMOS process; EDRX; IEEE 802.15.4g wireless sensor networks; address-detection FSK receiver; power 45.5 muW; power consumption minimization; receiver sensitivity; size 65 nm; ultra-low-power 2-step wake-up receiver; ultra-low-power energy-detection receiver; wakeup packet; Clocks; Frequency shift keying; IEEE 802.15 Standards; Interference; Power demand; Receivers; Sensitivity;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858382

Filename

6858382