A design methodology for logic paths tolerant to local intra-die variations

Process variations have become a critical issue influencing the performance of nanometer digital circuits at gigascale integration; variations are classified in two types: inter-die and intra-die. Whereas inter-die variations affect the deviation of performance distribution in a lot of chips, intra-die variations affect the media of performance distribution. The present work proposes a new design methodology for designing logic paths tolerant to local intra-die variations. A library of transistor structures with different degree of delay variability is defined. Transistors from the logic gates are replaced with these structures according to selection criteria to improve the delay tolerance to process variation on logic paths. Delay variability is reduced at the expense of circuit area. Results show a significant variability reduction for a moderate increment of area and power consumption.