DocumentCode
1832042
Title
Design and analysis of a multi-layer transformer balun for silicon RF integrated circuits
Author
Yang, H.Y.D. ; Zhang, L. ; Castaneda, J.A.
Author_Institution
Broadcom Corp., El Segundo, CA, USA
Volume
1
fYear
2002
fDate
2-7 June 2002
Firstpage
601
Abstract
In this paper, we present the design and analysis of an on-chip transformer balun for silicon RFIC. Both the primary and secondary spread over four metal layers along a common symmetric axis to reduce the overall area maintaining reasonable quality factor. A five port transformer balun circuit model is developed to facilitate the device simulation. A 4:11 transformer balun is fabricated and test. It is ideal for LNA to enhance the gain with optimum noise figure.
Keywords
Q-factor; baluns; elemental semiconductors; high-frequency transformers; monolithic integrated circuits; silicon; LNA; Si; five-port circuit model; gain; multi-layer transformer balun; noise figure; quality factor; silicon RF integrated circuit; Circuit simulation; Circuit testing; Costs; Impedance matching; Noise figure; Q factor; Radio frequency; Radiofrequency integrated circuits; Signal design; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium Digest, 2002 IEEE MTT-S International
Conference_Location
Seattle, WA, USA
ISSN
0149-645X
Print_ISBN
0-7803-7239-5
Type
conf
DOI
10.1109/MWSYM.2002.1011692
Filename
1011692
Link To Document