Fully digital AER convolution chip for vision processing

We present a neuromorphic fully digital convolution microchip for address event representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It operates on a pixel array of size 32 times 32, and the kernel is programmable and can be of arbitrary shape and size up to 32 times 32 pixels. The chip receives and generates data in AER format, which is asynchronous and digital. The paper describes the architecture of the chip, the test setup, and experimental results obtained from a fabricated prototype.