10-bit 100MS/s CMOS pipelined A/D converter with 0.59pJ/conversion-step

Author

Kim, Moo-Young ; Kim, Jinwoo ; Lee, Tagjong ; Kim, Chulwoo

Author_Institution

Dept. of Electr. & Electron. Eng., Korea Univ., Seoul

fYear

2008

fDate

3-5 Nov. 2008

Firstpage

65

Lastpage

68

Abstract

A 31 mW, 10-bit 100 MS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2 dB is measured with a 1 MHz input frequency. It has been implemented in a 0.18 um CMOS process and it occupies 1.6 x 0.8 mm² of active area.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; CMOS pipelined A-D converter; PVT condition detector; conversion-step; energy 0.59 pJ; frequency 1 MHz; opamp sharing technique; power 31 mW; size 0.18 mum; Analog-digital conversion; CMOS analog integrated circuits; CMOS digital integrated circuits; Energy consumption; Multimedia communication; Multimedia systems; Resistors; Solid state circuits; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-2604-1

Electronic_ISBN

978-1-4244-2605-8

Type

conf

DOI

10.1109/ASSCC.2008.4708730

Filename

4708730