A 66fps 3 8mW nearest neighbor matching processor with hierarchical VQ algorithm for real-time object recognition

Author

Kim, Joo-Young ; Kim, Kwanho ; Lee, Seungjin ; Kim, Minsu ; Yoo, Hoi-Jun

Author_Institution

Sch. of EECS, Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

2008

fDate

3-5 Nov. 2008

Firstpage

177

Lastpage

180

Abstract

A 66 fps 38 mW nearest neighbor matching processor for real-time object recognition has been fabricated in 0.13 mum CMOS technology. It consists of RISC processing core, pre-fetch DMA, and two independent sets of logic merged memories. Based on hierarchical vector quantization (H-VQ) algorithm, implemented processor achieves 22.5X cycle time reduction in matching process without any accuracy loss in VQ operation. As a result, 66 fps frame rate is obtained for QVGA (320times240 pixels) video images with 5632-entry database.

Keywords

CMOS memory circuits; image matching; object recognition; system-on-chip; vector quantisation; video signal processing; CMOS technology; RISC processing core; SoC; hierarchical VQ algorithm; logic merged memories; nearest neighbor matching processor; power 38 mW; pre-fetch DMA; real-time object recognition; size 0.13 mum; vector quantization algorithm; video images; Acceleration; Degradation; Hardware; Image coding; Image databases; Nearest neighbor searches; Object recognition; Real time systems; Solid state circuits; Vector quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-2604-1

Electronic_ISBN

978-1-4244-2605-8

Type

conf

DOI

10.1109/ASSCC.2008.4708757

Filename

4708757