DocumentCode
1833813
Title
MPEG2 decoding complexity regulation for a media processor
Author
Lan, John Tsehua ; Chen, Yingwei ; Zhong, Zhun
Author_Institution
Philips Res., Briarcliff Manor, NY, USA
fYear
2001
fDate
2001
Firstpage
193
Lastpage
198
Abstract
Current implementations of real-time video decoders employ hard-decoding without run-time computation regulation. The result is fluctuation in the video decoding time that requires over-specified dedicated hardware or general-purpose processors to guarantee real-time performance. We propose a computation regulation system for MPEG-2 video decoding on media processors that obviates over-engineering while maintaining real-time performance and video quality. Our computation regulation scheme consists of dynamic complexity prediction and control. The complexity prediction algorithm takes implementation issues specific to media processors into account and yields accurate prediction results that correlate with actual measurements to 97%. The predicted complexity is then used as a control signal to adjust the decoding algorithm so that peaks in computation load are suppressed. Simulation results show that our system can lower the overall CPU cycle budget by a large factor (25%) with very little degradation in video quality
Keywords
computational complexity; decoding; digital signal processing chips; video signal processing; CPU cycle budget; MPEG-2 decoding complexity regulation; computation load; computation regulation system; control signal; dynamic complexity prediction; media processor; real-time performance; real-time video decoders; video decoding; video quality; Computational modeling; Data mining; Decoding; Degradation; Fluctuations; Hardware; Parallel processing; Prediction algorithms; Predictive models; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia Signal Processing, 2001 IEEE Fourth Workshop on
Conference_Location
Cannes
Print_ISBN
0-7803-7025-2
Type
conf
DOI
10.1109/MMSP.2001.962733
Filename
962733
Link To Document