A low-jitter clock generator based on ring oscillator with 1/f noise reduction technique for next-generation mobile wireless terminals

Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). This paper describes a low jitter clock generator for next-generation mobile wireless terminals. The clock generator employs a novel slew rate balancing (SRB) circuit in a single-ended ring oscillator based VCO to suppress the VCO phase noise due to up-converted 1/f noise. The proposed clock generator is fabricated in a 90-nm CMOS technology. The measured results show that the SRB circuit reduces the VCO phase noise by 3-5 dB at the offset frequencies where the up-converted 1/f noise dominates. The clock generator achieves 3.0 ps rms integrated jitter. Required chip area is 0.18 mm² and the power consumption is 9 mW.