On the parallel MAP algorithm

Author

Akella, Ramakrishna ; Wolf, Jack Keil

Author_Institution

California Univ., San Diego, La Jolla, CA, USA

fYear

2001

fDate

2001

Firstpage

371

Lastpage

376

Abstract

The MAP algorithm used in turbo decoders is very parallelizable. This property can be used to speed them up. The speedup is attained at the expense of increased complexity and processing hardware. The increase in processing hardware is linear with the speedup but the increase in complexity of the parallel implementation compared to the traditional implementation is extremely small and this is the main observation of this paper. We discuss the parallel implementation of the MAP algorithm, the increase in complexity and memory and contrast the behaviour with that of the Viterbi algorithm. The results given here also suggest a change in design methodology of the sliding window implementation of turbo decoders

Keywords

computational complexity; iterative decoding; maximum likelihood decoding; parallel algorithms; turbo codes; MAP algorithm; complexity; iterative decoding; memory; parallel algorithm; processing hardware; sliding window implementation; speedup; turbo decoders; Computational complexity; Delay; Design methodology; Hardware; Iterative algorithms; Iterative decoding; Lifting equipment; Magnetic recording; Turbo codes; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Multimedia Signal Processing, 2001 IEEE Fourth Workshop on

Conference_Location

Cannes

Print_ISBN

0-7803-7025-2

Type

conf

DOI

10.1109/MMSP.2001.962762

Filename

962762