• DocumentCode
    1835024
  • Title

    Modelling microstructure development in trench-interconnect structures

  • Author

    Sanchez, John, Jr. ; Besser, Paul R.

  • Author_Institution
    Dept. of Mater. Sci. & Eng., Michigan Univ., Ann Arbor, MI, USA
  • fYear
    1998
  • fDate
    1-3 Jun 1998
  • Firstpage
    247
  • Lastpage
    249
  • Abstract
    The effects of surface and interfacial energies and trench geometry on microstructure evolution in damascene-processed interconnect structures are modelled. Grain growth and texture evolution are shown to depend on the magnitude of surface and interfacial energy variations with crystallographic orientation and with trench aspect ratio. Grain texture evolution in high aspect ratio trenches is driven by the minimization of grain sidewall interfacial energy, whereas the crystallographic evolution of grains within low aspect ratio structures is determined by more typical surface and lower interface energy minimization considerations. Comparisons are made to recent experimental results which characterize the development of crystallographic texture and grain size in damascene-processed interconnects
  • Keywords
    crystal orientation; grain growth; grain size; integrated circuit interconnections; integrated circuit metallisation; isolation technology; semiconductor process modelling; surface energy; surface texture; crystallographic evolution; crystallographic orientation; crystallographic texture; damascene-processed interconnect structures; damascene-processed interconnects; grain growth; grain sidewall interfacial energy; grain size; grain texture evolution; interface energy minimization; interfacial energy; interfacial energy variation; microstructure development modelling; microstructure evolution; surface energy; surface energy minimization; surface energy variation; trench aspect ratio; trench geometry; trench-interconnect structures; Annealing; Capacitive sensors; Crystallography; Grain size; Integrated circuit interconnections; Integrated circuit reliability; Microstructure; Minimization; Solid modeling; Surface texture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-4285-2
  • Type

    conf

  • DOI
    10.1109/IITC.1998.704912
  • Filename
    704912