Variability-aware design of subthreshold devices

Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks for digital subthreshold logic circuits. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this paper, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. By using the technique, a process/device designer can optimize a transistor for subthreshold operation in terms of the total leakage current and intrinsic delay bounds. Sample devices are optimized for 90 nm and 65 nm technologies, and Monte Carlo simulations verify the accuracy of the technique.