A 100 /spl mu/W, 20 Mcps versatile correlator chip for third generation WCDMA systems

This paper presents a low power, yet highly flexible correlator chip targeted at future WCDMA based systems. In addition to the correlator unit, the chip also integrates circuits for PN sequence generation, and internal chip/symbol clock generation. Moreover, the chip architecture provides the user (or user program) with a host of configuration options. These include: programmable chipping rate, programmable spreading factor, choice of M-, Gold-, or Kasami-sequences, variable length orthogonal code generation, and the ability to vary the internal precision in order to save power when a particular service has a low target SNR. The core unit of the correlator, the multiply-accumulator, adopts a biased number representation architecture and dissipates 100 micro-W when operating at 20 Mcps off of a 2 V supply. The chip has been fabricated in a 0.35 micron CMOS process and occupies a core area of 0.356 mm/sup 2/. The total power consumption of the chip is 650 /spl mu/W.