Estimating interconnect performance for a new National Technology Roadmap for Semiconductors

The advent of smaller submicron feature sizes for CMOS technology has led to ever increasing device speeds but has singled out interconnects (which do not scale well) as the limiting constraint for microelectronics technology. This has led to extensive research in alternative materials as well as wiring configurations needed for interconnects to catch up with increasing clock speeds. Improvements in interconnect technology alone, i.e. new materials and interconnect configurations, will not provide the high performance anticipated by the 1997 NTRS. Changes in chip architecture and circuits are also required. This is where an early performance estimator is valuable. Large design spaces can be explored without committing to a particular configuration. Using the Rensselaer Interconnect Performance Estimator (RIPE), we show that it is relatively easy to evaluate the performance of proposed designs