• DocumentCode
    1836463
  • Title

    Multibit incremental data converters with reduced sensitivity to mismatch

  • Author

    Mehrabi, Arash ; Ranjbar, Mohammad ; Oliaei, Omid

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    1436
  • Lastpage
    1439
  • Abstract
    Incremental data converters (IDC) can achieve absolute accuracies higher than 16 bits with very low power consumption. However, single-bit IDCs require numerous clock cycles per conversion. In this paper, the advantages of employing multibit quantizers for faster conversions are analyzed and a novel method for reducing the effect of element mismatch is presented.
  • Keywords
    clocks; convertors; quantisation (signal); clock cycles; element mismatch; low power consumption; multibit incremental data converters; multibit quantizers; Clocks; Delta-sigma modulation; Digital filters; Digital modulation; Energy consumption; Feeds; Linearity; Noise shaping; Quantization; Stability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    978-1-4244-1684-4
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4541698
  • Filename
    4541698
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1836463