Multi-clock pipeline structure for 802.11 a WLAN transceiver

The IEEE 802.11a standard is an attractive choice for wireless local-area networking (WLAN) because its 5 GHz band is less crowded than the alternative 2.4 GHz band. This work describes a hardware architecture for the digital part of the 802.11a physical layer. Our design features a multi-clock pipeline structure that allows for non-stop data flow. This leads to high throughput, low dynamic power consumption, and low overhead of switching between different data rates.