• DocumentCode
    1838270
  • Title

    Compact calibration circuit for large neuromorphic arrays

  • Author

    Lenero-Bardallo, Juan A. ; Serrano-Gotarredona, Teresa ; Linares-Barranco, Bernabe

  • Author_Institution
    Inst. de Microelectron. de Sevilla, Univ. de Sevilla, Sevilla
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    1776
  • Lastpage
    1779
  • Abstract
    Low current applications, like neuromorphic circuits, where operating currents can be as low as few nano amps or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precision. Here we present a new calibration approach based on individually calibrated current sources made with MOS transistors of digitally adjustable length, which require only N unit transistors. The scheme includes a translinear circuit based tuning scheme, which allows to expand the operating range of the calibrated circuits with graceful precision degradation, over 4 decades of operating currents. Experimental results are provided for 5-bit resolution DACs operating at 20 nA.
  • Keywords
    MOSFET; calibration; circuit tuning; MOS transistors; calibratable current sources; calibration approach; compact calibration circuit; current 20 nA; digitally adjustable length; neuromorphic arrays; transistor mismatches; translinear circuit; tuning scheme; CMOS process; Calibration; Circuit optimization; Degradation; Energy consumption; Joining processes; MOSFETs; Neuromorphics; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    978-1-4244-1684-4
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4541783
  • Filename
    4541783