DocumentCode
1838324
Title
Design of multiple-valued linear digital circuits for highly parallel unary operations
Author
Nakajima, Masami ; Kameyama, Michitaka
Author_Institution
Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan
fYear
1993
fDate
24-27 May 1993
Firstpage
283
Lastpage
288
Abstract
A design method for highly parallel multiple-valued linear digital circuits for unary operations using the concept of a cycle and a tree is proposed. In the circuit design, an analytical approach using a representation matrix is possible, so that the search procedure for optimal locally computable circuits becomes very simple. Some examples are shown to demonstrate the usefulness of the design algorithm
Keywords
logic circuits; many-valued logics; parallel architectures; highly parallel; linear digital circuits; multiple-valued; representation matrix; search procedure; unary operations; Adders; Circuit synthesis; Combinational circuits; Concurrent computing; Design methodology; Digital circuits; Digital systems; Input variables; Integrated circuit interconnections; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
Conference_Location
Sacramento, CA
Print_ISBN
0-8186-3350-6
Type
conf
DOI
10.1109/ISMVL.1993.289546
Filename
289546
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