DocumentCode
1838648
Title
Structured LDPC codes with low error floor based on PEG tanner graphs
Author
Lin, YiKai ; Chen, ChihLung ; Liao, YenChin ; Chang, HsieChia
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
fYear
2008
fDate
18-21 May 2008
Firstpage
1846
Lastpage
1849
Abstract
Progressive edge-growth (PEG) algorithm was proven to be a simple and effective approach to design good LDPC codes. However, the Tanner graph constructed by PEG algorithm is non-structured which leads the positions of l´s of the corresponding parity check matrix fully random. In this paper, we propose a general method based on PEG algorithm to construct structured Tanner graphs. These hardware-oriented LDPC codes can reduce the VLSI implementation complexity. Similar to PEG method, our CP-PEG approach can be used to construct both regular and irregular Tanner graphs with flexible parameters. For the consideration of encoding complexity and error floor, the modifications of proposed algorithm are discussed. Simulation results show that our codes, in terms of bit error rate (BER) or packet error rate (PER), outperform other PEG-based LDPC codes and are better than the codes in IEEE 802.16e.
Keywords
parity check codes; LDPC codes; low error floor; progressive edge-growth algorithm; structured Tanner graph; Algorithm design and analysis; Bit error rate; Block codes; Encoding; Error analysis; Floors; Iterative decoding; Parity check codes; Sparse matrices; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4541800
Filename
4541800
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