Current-mode image sensor with 1.5 transistors per pixel and improved dynamic range

This paper describes a current-mode active pixel sensor (APS) for low supply voltage, low noise and high resolution/high speed imaging applications. The imager is designed in a standard 0.25 mum 2.5 V CMOS process. A transistor count of 1.5 per pixel is achieved through transistor sharing and floating diffusion (FD) based addressing. Highly linear current readout in velocity saturation, as well as triple sampling (TS), are used to reduce fixed pattern noise (FPN). Dynamic range (DR) is improved through FD presetting and boosting techniques, which allow the full-well capacity of photodiodes to be utilized without degrading readout linearity. Post-extraction simulation results on FPN and DR are presented, and compared favorably to a conventional 3-transistor pixel design.