Novel test structures for the investigation of the efficiency of guard rings used for I/O-latch-up prevention

Author

Quincke, J.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1990

fDate

5-7 March 1990

Firstpage

35

Lastpage

39

Abstract

Test structures for guard ring efficiency measurements concerning input/output (I/O) latchup in integrated CMOS circuits for minority and majority carrier injection are introduced. The locations of two guard rings are varied for n/n/sup +/-epi (epitaxial) material and n-substrate. Latchup measurements were taken using a worst case detector, which simulates neighboring internal logic circuits. In non-epi material, the total efficiency of substrate guard rings for majority carrier injection, and of well guard rings for minority carrier injection is nearly equal (factor for the trigger current approximately=20). For epi material, the substrate guard rings for majority carrier injection have very little influence; but the trigger current without guard rings is already 25 times higher than for non-epi material.<>

Keywords

CMOS integrated circuits; integrated circuit technology; integrated circuit testing; I/O-latch-up prevention; epitaxial material; guard ring efficiency measurements; integrated CMOS circuits; latchup characterisation test structures; majority carrier injection; minority carrier injection; nonepitaxial material; simulates neighboring internal logic circuits; substrate guard rings; test structures; trigger current; well guard rings; worst case detector; Charge carriers; Circuit simulation; Circuit testing; Detectors; Integrated circuit measurements; Integrated circuit reliability; Logic circuits; Substrates; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/ICMTS.1990.67876

Filename

67876