DocumentCode
1839710
Title
A ±1 V four-quadrant analog BiCMOS multiplier
Author
Lee, S.T. ; Yeo, K.S. ; Rofail, Samir S. ; Lau, K.T.
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
fYear
1995
fDate
24-28 Oct 1995
Firstpage
772
Lastpage
774
Abstract
A ±1 V four-quadrant analog BiCMOS multiplier is presented. The design is based on the current-mode approach and uses the square-law characteristics of a MOS transistor in saturation. The new multiplier utilizes I-V converters, current-mirrors, and only two power supplies to achieve high linearity and superior performance
Keywords
BiCMOS analogue integrated circuits; analogue multipliers; integrated circuit design; 1 V; I-V converters; MOS transistor; current mirrors; current-mode design; four-quadrant analog BiCMOS multiplier; linearity; low voltage circuit; power supplies; saturation; square-law characteristics; BiCMOS integrated circuits; Circuit simulation; Circuit testing; Frequency; Linearity; Low voltage; MOSFETs; Power engineering and energy; Total harmonic distortion; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location
Beijing
Print_ISBN
0-7803-3062-5
Type
conf
DOI
10.1109/ICSICT.1995.503555
Filename
503555
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