ESD protection devices placed inside keep-out zone (KOZ) of through Silicon Via (TSV) in 3D stacked integrated circuits

Through Silicon Via (TSV) has been utilized in vertically stacking IC dice to implement real system-in-chip applications. However, threshold voltage and mobility of MOSFETs can be influenced by induced mechanical strain of the TSV, causing degradation or non-stability of functional circuits. Therefore, a Keep-out Zone (KOZ) is defined, meaning that active devices are forbidden in this area. This paper investigates the impact on ESD protection devices placed inside this KOZ in bulk FinFET process.