Error Correction in On-Wafer Harmonic Power Measurements

This paper presents a simple method for correcting errors in on-wafer harmonic power measurements due to non-50 ¿ port impedances and network losses. To correct for losses and mismatches and to calculate the equivalent 50 ¿ power levels at the fundamental and harmonic frequencies, the formulation makes use of vector S-parameter characterization of the test system and the DUT. The 50 ¿ correction is valid under "quasi-linear" conditions where the device S-parameters can be approximated by their small signal value. This approximation is examined using harmonic balance simulation of a nonlinear FET model. Under large signal conditions where the "quasi-linear" assumption can no longer be made, correction for losses and mismatch is provided for in the formulation, however, only the net power delivered to the non-50 ¿ load can be calculated in this case. We illustrate the correction method with harmonic power measurements of a 0.25 ¿m × 160 ¿m pHEMT and a 0.25 ¿m × 400 ¿m MESFET. The corrected fundamental power is seen to be in direct agreement with the measured 50 ¿ transducer gain (i.e., S21) of the device. The correction also improves the fit between non-linear model simulation of the fundamental, second and third harmonic power levels and those of measured data.