A Coverage-Driven Verification Platform for Evaluating NoC Performance and Test Structure

NoC (Network-on-Chip) has been proposed as a new solution to deal with the global communication problem of complex SoC(System-on-Chip). An evaluation tool is essential for optimizing the NoC design, through which the functionality and performance of the NoC are verified. This paper presents a coverage-driven and hierarchical NoC verification platform based on System Verilog language. It is applicable to various NoCs with arbitrary size, topology, multiple interface protocols and various test structure. To verify the effectiveness of this platform, Mesh and Totus topology and the corresponding XY or TXY routing algorithms were adopted and applied to random uniform and random hot distribution simultaneously. Furthermore, the platform is also applied for evaluating different test schemes. The results of performance and test structure evaluation show that the verification platform improves the verification efficiency and has good adaptability and scalability as well.