SPEED: synthesis of high-performance large scale analog/mixed signal circuit

Simulation-based cell level analog synthesis tools have been successfully proven by chip fabrication. Application of these synthesis approaches to larger circuits with high accuracy has been difficult due to two limitations: 1) large design space, 2) long simulation time. This paper addresses these limitations using a systematic methodology SPEED, simulation plus equation-based synthesis, to size the first two multiplying and sub-DAC stages in a 13-bit 40-MSample/s pipelined analog to digital converter for minimum power consumption. The resulting chip, which had a measured signal to noise ratio of 73.8dB and consumed 364mW @ 3.3V proves the efficacy of the proposed synthesis approach.